1. Field of the Invention
The present invention relates to a method of fabricating a dynamic random access memory (DRAM), and particularly to a method of fabricating node capacitor for DRAM processes.
2. Description of the Prior Art
Recently, demand for semiconductor devices has rapidly increased owing to widespread use of electronic equipment. In particular, the increasing popularity of some electronic equipment such as computers, for example, is increasing the demand for large semiconductor memories. One approach for increasing capacitance while maintaining the high integration of the storage cells is directed toward the shape of the capacitor electrodes. In this approach, the polysilicon layer implementing a capacitor electrode may have protrusions, fins, cavities, etc., to increase the electrode's surface area, thereby increasing the capacitor's capacitance while maintaining the small area occupied by the capacitor on the substrate surface. Consequently, this type of capacitor has come to be widely used in DRAM devices.
In another approach, a hemispherical grain (HSG) technique is used to increase the surface area of the capacitor electrode. FIG. 2 shows the cross section of a traditional DRAM capacitor fabricated using a hemispherical grain (HSG) technique. A hemispherical grain polysilicon layer 210 is deposited on a doped polysilicon storage node 200. Thus, the topography of the hemispherical grain polysilicon layer 210 is transferred to the top surface of the doped polysilicon storage node 200, forming a bottom electrode, as shown in FIG. 2. Although this DRAM capacitor has some increase in electrode surface area resulting from the rugged surface of the doped polysilicon storage node 200, further increases in electrode surface area are still desirable.